In a conventional direct-conversion type wireless receiver (hereinafter, referred to as a DC type wireless receiver), in which a received signal is frequency-converted by a mixer into a base band signal that is a modulated wave and the base band signal is amplified to a required signal level for demodulation by a differential amplifier, an input signal obtained by inputting a local signal into the mixer by using a local oscillator leaks to the RF input port of the mixer, and the leakage signal is reflected back from an antenna or a low-noise amplifier to be re-inputted into the mixer. Accordingly, since the re-inputted signal is identical to the local signal, a self-mixing occurs to thereby generate a DC offset.
In the DC type wireless receiver, the DC level of an input signal inputted into a demodulation unit is amplified in proportion to the value of DC offset×Gain since IQ signal includes the DC offset. Accordingly, since the DC bias exceeds the power supply voltage, there is a problem in that a desired signal cannot be transmitted. For this reason, the DC offset is required to be corrected to a level such that no such problem is encountered even when the DC level is amplified in proportion to the value of the gain.
In order to correct the DC offset, Japanese Patent Application Publication H10-013482 discloses a technique for detecting and correcting the DC offset.
FIG. 10 shows a conventional direct-conversion receiver. This receiving circuit includes an antenna 1, a band pass filter 2, a low noise amplifier 3, mixers 4 and 5, a phase shifter 6, a local oscillator 7, DC offset correction circuits 40 and 41, low pass filters 18 and 19, variable gain amplifiers 20 and 21, an automatic gain control unit 22, and a demodulation unit 23.
A desired radio frequency of a received signal only passes through the band pass filter 2, and the received signal is amplified by the low noise amplifier 3 and then is inputted into the mixers 4 and 5. The received signal is frequency-converted to a base band signal by the mixer 4 (or 5) by using a local signal of the local oscillator 7. The base band signal is amplified by the differential amplifier 14 (or 15) provided in the next stage, and a reception channel frequency is selected through the low pass filter 18 (or 19). Thereafter, a gain of the signal is adjusted by the automatic gain control unit 22 and the variable gain amplifier 20 (or 21) depending on the received signal strength in order to secure a dynamic range performance. The signal is then inputted into the demodulation unit 23. Since DC offsets generated by the mixers 4 and 5 and the differential amplifiers 14 and 15 are added to the base band signals, and then inputted into the demodulation unit 23, the DC offset correction circuits 40 and 41 are provided to correct the DC offsets.
In the conventional case, the DC offset correction circuit 40 (or 41), which includes an AD converter 24 (or 25), a DA converter (hereinafter, referred to as DAC) 32 (or 33), an operational amplifier 34 (or 35), a comparator 28 (or 29), a reference voltage code 26 (or 27), and a counter control unit 30 (or 31), corrects the DC offset by changing an output voltage of the operational amplifier 34 (or 35).
If an output voltage of the positive side of the differential output of the mixer 4 (or 5) is Vp; an output voltage of the negative side of the differential output of the mixer 4 (or 5) is Vn; an output voltage of the signal component of the positive side is Vpdata; an output voltage of the DC component other than the signal component of the positive side (bias voltage+DC offset) is Vpdc; an output voltage of the signal component of the negative side is Vndada; and an output voltage of the DC component other than the signal component of the negative side is Vndc, Vp and Vn are expressed as the following equations:Vp=Vpdata+Vpdc, andVn=Vndata+Vndc.
If an output voltage of the operational amplifier 34 (or 35) is V′ and an output voltage of the differential amplifier 14 (or 15) is Vout, Vpdc becomes equal to Vndc when no DC offset is generated, and thus, the output voltage Vout is expressed as the following equation (a):
                                                        Vout              =                            ⁢                                                (                                      R                    ⁢                                                                                  ⁢                    2                    ⁢                                                                  (                                                  Vp                          -                          Vn                                                )                                            /                      R                                        ⁢                                                                                  ⁢                    1                                    )                                +                                  V                  ′                                                                                                        =                            ⁢                                                (                                      R                    ⁢                                                                                  ⁢                    2                    ⁢                                                                  (                                                  Vpdata                          -                          Vndata                                                )                                            /                      R                                        ⁢                                                                                  ⁢                    1                                    )                                +                                                      V                    ′                                    .                                                                                        (        a        )            
If the DC offset generated by the mixer 4 (or 5) is α (=Vpdc−Vndc), the output voltage Vout of the differential amplifier 14 (or 15) is expressed as the following equation (b):
                                                        Vout              =                            ⁢                                                (                                      R                    ⁢                                                                                  ⁢                    2                    ⁢                                                                  (                                                  Vpdata                          -                          Vndata                          +                          α                                                )                                            /                      R                                        ⁢                                                                                  ⁢                    1                                    )                                +                                  V                  ′                                                                                                        =                            ⁢                                                (                                      R                    ⁢                                                                                  ⁢                    2                    ⁢                                                                  (                                                  Vpdata                          -                          Vndata                                                )                                            /                      R                                        ⁢                                                                                  ⁢                    1                                    )                                +                                  R                  ⁢                                                                          ⁢                                      2                    ·                                          α                      /                      R                                                        ⁢                                                                          ⁢                  1                                +                                                      V                    ′                                    .                                                                                        (        b        )            
Here, R2·α/R1 is the voltage generated by the DC offset. If a bias voltage after the differential amplifier 14 (or 15) is Vref, the DC offset is corrected by controlling V′ so as to satisfy the following equation (c):Vref=R2·α/R1+V′  (c).
Correction of the DC offset is controlled when the mixer 4 (or 5) outputs only DC component output voltages Vpdc and Vndc, and the automatic gain control unit 22 controls the variable gain amplifier 20 (or 21) to be fixed to a maximum gain in order to efficiently use the resolution of the ADC 24 (or 25). Then, the counter control is started by using an initial signal (DcIni signal) 38 outputted from the CPU or the like as a trigger.
FIG. 11 shows a timing chart showing a DAC code, an ADC code, and an output of the comparator 28 (or 29) from the beginning to the end of the control performed by the counter control unit 30 (or 31) after the DcIni signal 38 is inputted.
The counter of the counter control unit 30 (or 31) is reset by the DcIni signal 38 and synchronized with a clock outputted from a clock generation unit 39. The counter is increased when an enable signal inputted into the counter control unit 30 (or 31) is “1” and is not increased when the enable signal is “0.” The DAC 32 (or 33) outputs voltage V′ in accordance with the counter value (DAC code) of the counter control unit 30 (or 31) and controls the voltage Vout.
The reference voltage code 26 (or 27) is same (same value) as the code outputted when the voltage Vref is inputted into the ADC 24 (or 25). The comparator 28 (or 29) compares the reference voltage code 26 (or 27) with the output code from the ADC 24 (or 25). Then, the comparator 28 (or 29) outputs “0” if the reference voltage code 26 (or 27) is smaller than or equal to the ADC code (reference voltage code≦ADC code) and “1” if the reference voltage code 26 (or 27) is larger than the ADC code (reference voltage code>ADC code).
The ADC code satisfies “ADC input voltage ≈ Vref” when the output of the comparator 28 (or 29) is changed from “1” to “0”. Therefore, the DC offset is corrected by stopping the counter operation of the counter control unit 30 (or 31) when the output of the comparator 28 (or 29) is changed to “0.”
A voltage control range of the DAC 32 (or 33) performing the correction of the DC offset is set to be wider than the possible voltage range of the DC offset, and the DAC 32 (or 33) has a higher resolution than the desired correction range. Further, the ADC 24 (or 25), which detects the correction of the DC offset, has a higher resolution than the desired correction range. The clock, which drives the counter control unit 30 (or 31), is operated at a frequency lower than the settling time of step response between the DAC 32 (or 33) and the ADC 24 (or 25).
In the method of correcting a DC offset described in Japanese Patent Application Publication H10-013482, since noises are included in the output voltage of the operational amplifier at the output port of the DC offset correction circuit, the receiver sensitivity is degraded. In addition, since the operation of correcting the DC offset is required to be processed at a high speed, there is required a control unit capable of correcting the DC offset at a high speed.